Über die Berechnung der Stoßspannungsverteilung in Maschinenwicklungen

Übersicht Es wird ein Berechnungsverfahren für die Bestimmung der Stoßspannungsverteilung in Maschinenwicklungen mit induktiven Kopplungen angegeben. Die Lösung des für die Spannungsverteilung des Ersatzschemas aufgeschriebenen und in Matrizenform erhaltenen Differentialgleichungssystems zweiter Ordnung ergibt sich in geschlossener Form. Das Problem führt zur verallgemeinerten Eigenwertaufgabe von Matrizen.

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Contents The paper describes a procedure for calculating the impulse voltage distribution in rotating-machine windings having mutual inductance between the winding sections. The investigations has resulted in an exact closed-form solution of the governing matrix differential equation of the equivalent circuit used in the calculations. The method used in the investigations lead to the so called generalized eigenvalue problem.

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D. Kerényi, Ganz Elektrotechnische Werke, Budapest II. Lövház u. 39. Dr.P. Rózsa, Zentralforschungsinstitut für Physik der Ungarischen Akademie der Wissenschaften, Budapest XII, Ungarn, Konkoly Thege út.     

Über die Berechnunǵ der Stoßspannunǵsverteilunǵ in Maschinenwicklunǵen

Ohne Zusammenfassung     

Design on the low-leakage diode string for using in the power-railESD clamp circuits in a 0.35-μm silicide CMOS process

A new design of the diode string with very low leakage current is proposed for use in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the leakage current of this new diode string with six stacked diodes at 5 V (3.3 V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125°C in a 0.35 μm silicide CMOS process, whereas the previous designs have a leakage current in the order of mA. The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35 μm silicide CMOS process by using neither ESD implantation nor the silicide-blocking process modifications     

A state prediction scheme for discrete time nonlinear dynamic systems

A state prediction scheme is proposed for discrete time nonlinear dynamic systems with non-Gaussian disturbance and observation noises. This scheme is based upon quantization, multiple hypothesis testing, and dynamic programming. Dynamic models of the proposed scheme are as general as dynamic models of particle predictors, whereas the nonlinear models of the extended Kalman (EK) predictor are linear with respect to the disturbance and observation noises. The performance of the proposed scheme is compared with both the EK predictor and sampling importance resampling (SIR) particle predictor. Monte Carlo simulations have shown that the performances of the proposed scheme, EK predictor, and SIR particle predictor are all model-dependent, that is, one performs better than the others for a given example. Some examples, for which the proposed scheme performs better than the others do, are also given in the paper.     

ESD-Protection Design With Extra Low-Leakage-Current Diode String for RF Circuits in SiGe BiCMOS Process

Two low-leakage resistor-shunted diode strings are developed for use as power clamps in silicon-germanium (SiGe) BiCMOS technology. The resistors are used to bias the deep N-wells, significantly reducing the leakage current from the diode string. A methodology for selecting the values of the bias resistors is presented. For further reduction of the leakage current, an alternate design is presented: the resistor-shunted trigger bipolar power clamp. The power-clamp circuits presented herein may be used in cooperation with small double diodes at the I/O pins to achieve whole-chip electrostatic-discharge protection for RF ICs in SiGe processes     

EFFECTS OF HYDROCARBON LIQUID FEED IN POLYETHYLENE POLYMERIZATION PROCESS ON PARTICLE SURFACE TEMPERATURE

In the fluidized bed gas phase polymerization of polyethylene (PE), the heat generated by the exothermic polymerization process is dissipated into the gas mixture flowing past the polymer particles. The polymer particle temperature is determined by the extent of convective heat transfer and other mechanisms of heat removal. In addition to the heat removal by convective heat transfer, liquid hydrocarbon (HC) is often injected into the reactor to further remove heat by evaporation but without partaking in the reaction. The effects of adding this liquid HC on the particle surface temperature have been investigated numerically by means of a one-dimensional polar model. Results indicate that the primary mechanism for removal of the heat of polymerization from the particles is by means of convective heat transfer to the bulk gas, which amounts to 99.5% removal of total heat of polymerization. The PE particle temperature rises only by 1-2°C above the surrounding bed gas mixture. The addition of liquid HC to the feed, however, has a pronounced effect on controlling the reactor gas temperature as most of this liquid is evaporated to the gaseous phase before it reaches the polymer particles. To state it clearly, heat of polymerization is transferred from the particles to the reactor bulk gas predominantly by convection, and part of this heat is subsequently absorbed by evaporation of the fresh liquid HC in the feed. Comparison with a detailed computational fluid dynamic (CFD) model of polymerization in a generic gas phase reactor has also been conducted. The results confirm that the particle temperature rise above the reactor gas temperature is consistent with the one-dimensional model. However, local gas temperature variations are present in the reactor due to the unsteady gas-solid hydrodynamics. Hence, there are some zones that are a few degrees hotter/colder than the bulk reactor temperature with corresponding increase/decrease in particle temperature in these zones.     

Electrostatic discharge (ESD) protection for CMOS output buffers in scaled-down VLSI technology

To provide area-efficient output ESD protection for the scaled-down CMOS VLSI, a new output ESD protection is proposed. In the new output ESD protection circuit, there are two novel devices, the PTLSCR (PMOS-trigger lateral SCR) and the NTLSCR (NMOS-trigger lateral SCR). The PTLSCR is in parallel and merged with the output PMOS, and the NTLSCR is in parallel and merged with the output NMOS, to provide area-efficient ESD protection for CMOS output buffers. The trigger voltages of PTLSCR and NTLSCR are lowered below the breakdown voltages of the output PMOS and NMOS in the CMOS output buffer. The PTLSCR and NTLSCR are guaranteed to be turned on first before the output PMOS or NMOS are broken down by the ESD voltage. Experimental results have shown that the PTLSCR and NTLSCR can sustain over 4000 V (700 V) of the human-body-model (machine-model) ESD stresses within a very small layout area in a 0.6 μm CMOS technology with LDD and polycide processes. The noise margin of the proposed output ESD protection design is greater than 8 V (lower than −3.3 V) to avoid the undesired triggering on the NTLSCR (PTLSCR) due to the overshooting (undershooting) voltage pulse on the output pad when the IC is under normal operating conditions with 5 V VDD and 0 V VSS power supplies.     

ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness

A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 /spl mu/m/0.5 /spl mu/m has been successfully improved from the original 450 V to become 675 V in a 0.25-/spl mu/m CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 /spl mu/m/0.5 /spl mu/m for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation method with the n-type impurity can be fully merged into the general subquarter-micron CMOS processes.     

Substrate-triggered ESD protection circuit without extra process modification

A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole ESD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 /spl mu/m can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-/spl mu/m salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V//spl mu/m/sup 2/ of ggnMOS to 1.73 V//spl mu/m/sup 2/.